As the state of memory devices and other digital devices continues to evolve, the operating speeds of such devices has continued to increase. However. various factors may limit the speed at which such devices may operate. For example, signal line capacitance may limit the rate at which voltages on signal lines may change, thereby limiting the speed at which the line may be driven from a first logic level to a second logic level. If a signal transmitted over the line has not had time to reach a voltage level that can be detected as the second logic level, a data error may occur. Therefore, the operating speed of digital devices may be limited by the need to provide sufficient time for signals to propagate through signal lines.
Another goal in the development of memory devices and other digital devices is to minimize the power consumed by such devices. Such devices may increasingly be portable and thus powered by batteries, so reducing power consumption has the desirable effect of increasing the period of time that the device may be used between battery charges. Even if the amount of battery life between charges is not a consideration, minimizing power consumption may have the desirable effect of minimizing the amount of heat generated by the device. One conventional approach to minimizing power dissipation is to minimize the voltage difference between binary logic levels. As a result, the change in voltage when transitioning from one logic level to another is decreased. This reduced voltage change has the effect of reducing power consumption since transistors used in logic circuits conventionally dissipate substantially more power when switching between logic levels.
Unfortunately, the goal of maximizing operating speed may inherently conflict with the goal of minimizing power consumption. As the voltage differential between logic levels is decreased for the purpose of reducing power consumption, the time required to transition from a voltage corresponding to one logic level to a voltage that can be detected as corresponding to another logic level may increase, thereby limiting operating speed. Thus, there is often a tradeoff between power consumption and operating speed. This tradeoff may become more problematic when coupling digital signals through longer signal lines because longer signal lines tend to create higher line capacitances. For example, global input/output lines in a memory device may extend to a large number of memory arrays, thereby resulting in substantial line capacitance. It can therefore be difficult to minimize power consumption of memory devices and, at the same time, increase to operating speed of memory devices.